82801CA Datasheet, PDF (288/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.23
GEN_STA—General Status Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
D4h– D7h
00000F0Xh (upon RTCRST#
assertion low)
00002F0Xh (if Safe Mode
Strap is active)
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core(0:7), RTC (8:15)
Bit
Description
31:14 Reserved.
TOP_SWAP—R/W.
0 = ICH3 will not invert A16. This bit is cleared by RTCRST# assertion, but not by any other type of
13
reset.
1 = ICH3 will invert A16 for cycles targeting FWH BIOS space (Does not affect accesses to FWH
feature space).
Enables Processor BIST (CPU_BIST_EN)—R/W.
0 = Disable.
12 ^{1 = The INIT# signal will be driven active when CPURST# is active. INIT# will go inactive with the}
same timings as the other Processor I/F signals (Hold Time after CPURST# inactive). Note that
CPURST# is generated by the memory controller hub, but the ICH3 has a hub interface special
cycle that allows the ICH3 to control the assertion/deassertion of CPURST#.
Processor Frequency Strap (FREQ_STRAP[3:0])—R/W.
These bits determine the internal frequency multiplier of the processor. These bits can be reset to
11:8 ^{1111 based on an external pin strap or via the RTCRST# input signal. Software must program this}
field based on the processor’s specified frequency. Note that this field is only writable when the
SAFE_MODE bit is cleared to zero, and SAFE_MODE is only cleared by PWROK rising edge.
These bits are in the RTC well.
7:3 Reserved.
SAFE_MODE—RO.
2 ^{0 = ICH3 sampled AC_SDOUT low on the rising edge of PWROK.}
1 = ICH3 sampled AC_SDOUT high on the rising edge of PWROK. ICH3 will force
FREQ_STRAP[3:0] bits to all 1s (safe mode multiplier).
NO_REBOOT—R/W (special).
0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO timeout). This bit can not be set
1
to 0 by software if the strap is set to No Reboot.
1 = ICH3 will disable the TCO Timer system reboot feature. This bit is set either by hardware when
SPKR is sampled high on the rising edge of PWROK, or by software writing a 1 to the bit.
0 Reserved.
288
Intel^® 82801CA ICH3-S Datasheet