82801CA Datasheet, PDF (47/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
Table 2-11. Processor Interface Signals (Continued)
Name
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPUPWRGD
Type
O
O
O
O
O
I
I
OD
Description
Initialization: INIT# is asserted by the ICH3 for 16 PCI clocks to reset the
processor. ICH3 can be configured to support CPU BIST. In that case, INIT# will
be active when PCIRST# is active.
Processor Interrupt: INTR is asserted by the ICH3 to signal the processor that
an interrupt request is pending and needs to be serviced. It is an asynchronous
output and normally driven low.
Speed Strap: During the reset sequence, ICH3 drives INTR high if the
corresponding bit is set in the FREQ_STRP Register.
Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt to the
processor. The ICH3 can generate an NMI when either SERR# or IOCHK# is
asserted. The processor detects an NMI when it detects a rising edge on NMI.
NMI is reset by setting the corresponding NMI source enable/disable bit in the
NMI Status and Control Register.
Speed Strap: During the reset sequence, ICH3 drives NMI high if the
corresponding bit is set in the FREQ_STRP Register.
System Management Interrupt: SMI# is an active low output synchronous to
PCICLK. It is asserted by the ICH3 in response to one of many enabled
hardware or software events.
Stop Clock Request: STPCLK# is an active low output synchronous to
PCICLK. It is asserted by the ICH3 in response to one of many hardware or
software events. When the processor samples STPCLK# asserted, it responds
by stopping its internal clock.
Keyboard Controller Reset CPU: The keyboard controller can generate INIT#
to the processor. This saves the external OR gate with the ICH3’s other sources
of INIT#. When the ICH3 detects the assertion of this signal, INIT# is generated
for 16 PCI clocks.
Note that the ICH3 will ignore RCIN# assertion during transitions to the S1, S3,
S4 and S5 states.
A20 Gate: From the keyboard controller. Acts as an alternative method to force
the A20M# signal active. Saves the external OR gate needed with various other
PCIsets.
CPU Power Good: Should be connected to the processor’s PWRGOOD input.
This is an open-drain output signal (external pull-up resistor required) that
represents a logical AND of the ICH3’s PWROK and VRMPWRGD signals.
Intel^® 82801CA ICH3-S Datasheet
47