82801CA Datasheet, PDF (53/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
2.20.2 External RTC Circuitry
To reduce RTC well power consumption, the ICH3 implements an internal oscillator circuit that is
sensitive to step voltage changes in VccRTC and VBIAS. Figure 2-2 shows the circuitry required
to condition these voltages to ensure correct operation of the ICH3 RTC.
Figure 2-2. Required External RTC Circuit
3.3 V
VCCSUS
1 kΩ
1 µF
VCCRTC
Vbatt
1 kΩ
32768 Hz
Xtal
C1
0.047 uF
C3
12.5 pF
Note: Capacitor C2 and C3 values
are crystal-dependent.
C2
12.5 pF
RTCX2
R1
10 MΩ
RTCX1
R2
10 MΩ
VBIAS
VSSRTC
2.20.3 V5REF / Vcc3_3 Sequencing Requirements
V5REF is the reference voltages for 5 V tolerance on inputs to the ICH3. V5REF must be powered
up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must be powered down after
Vcc3_3 or before Vcc3_3 within 0.7 V. The rule must be followed to ensure the safety of the ICH3.
Caution: If this rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes
from the Vcc3_3 rail.
Figure 2-3 shows a sample implementation of how to satisfy the V5REF/3.3 V sequencing rule.
This rule also applies to the standby rails, but in most platforms, the VccSus3_3 rail is derived from
the VccSus5 and therefore, the VccSus3_3 rail will always come up after the VccSus5 rail. As a
reulst, V5REF_Sus will always be powered up before VccSus3_3. In platforms that do not derive
the VccSus3_3 rail from the VccSus5 rail, this rule must be comprehended in the platform design.
Intel^® 82801CA ICH3-S Datasheet
53