82801CA Datasheet, PDF (303/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.2.8
9.2.9
9.2.10
DMA Clear Byte Pointer Register
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Ch;
Ch. #4–7 = D8h
xxxx xxxx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
Clear Byte Pointer—WO. No specific pattern. Command enabled with a write to the I/O port address.
Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch
7:0
used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is
also cleared by part reset and by the Master Clear command. This command precedes the first
access to a 16 bit DMA controller register. The first access to a 16 bit register will then access the
significant byte, and the second access automatically accesses the most significant byte.
DMA Master Clear Register
I/O Address:
Default Value:
Ch. #0–3 = 0Dh;
Ch. #4–7 = DAh
xxxx xxxx
Attribute:
WO
Size:
8-bit
Bit
Description
Master Clear—WO. No specific pattern. Enabled with a write to the port. This has the same effect as
7:0 the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are cleared
and the Mask Register is set.
DMA_CLMSK—DMA Clear Mask Register
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Eh;
Ch. #4–7 = DCh
xxxx xxxx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
7:0 Clear Mask Register—WO. No specific pattern. Command enabled with a write to the port.
Intel^® 82801CA ICH3-S Datasheet
303