82801CA Datasheet, PDF (93/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.4.1.2
5.4.2
5.4.3
5.4.3.1
Rotating Priority
Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the last
channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).
Channels 0–3 rotate as a group of 4. They are always placed between Channel 5 and Channel 7 in
the priority list.
Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three positions in
the rotation, while channel group (0–3) comprises the fourth position in the arbitration.
Address Compatibility Mode
Whenever the DMA is operating, the addresses do not increment or decrement through the high-
and low-page registers. Therefore, if a 24-bit address is 01FFFFh and increments, the next address
will be 010000h, not 020000h. Similarly, if a 24-bit address is 020000h and decrements, the next
address will be 02FFFFh, not 01FFFFh. This is compatible with the 82C37 and page register
implementation used in the PC-AT. This mode is set after CPURST is valid.
Summary of DMA Transfer Sizes
Table 5-8 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word
Count Register” indicates that the register contents represents either the number of bytes to transfer
or the number of 16-bit words to transfer. The column labeled “Current Address Increment/
Decrement” indicates the number added to or taken from the current address register after each
DMA transfer cycle. The DMA channel mode register determines if the current address register
will be incremented or decremented.
Address Shifting When Programmed for 16-Bit I/O Count by Words
Table 5-8. DMA Transfer Size
DMA Device Date Size And Word Count
8-Bit I/O, Count By Bytes
16-Bit I/O, Count By Words (Address Shifted)
Current Byte/Word Count
Register
Bytes
Words
Current Address
Increment/Decrement
1
1
The ICH3 maintains compatibility with the implementation of the DMA in the PC AT that used the
82C37. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note
that the least significant bit of the low-page register is dropped in 16-bit shifted mode. When
programming the current address register (when the DMA channel is in this mode), the Current
Address must be programmed to an even address with the address value shifted right by one bit.
The address shifting is shown in Table 5-9.
Table 5-9. Address Shifting in 16-Bit I/O DMA Transfers
Output
Address
A0
A[16:1]
A[23:17]
8-Bit I/O Programmed Address
(Ch 0–3)
A0
A[16:1]
A[23:17]
16-Bit I/O Programmed Address
(Ch 5–7)
(Shifted)
0
A[15:0]
A[23:17]
NOTE: The least significant bit of the page register is dropped in 16-bit shifted mode.
Intel^® 82801CA ICH3-S Datasheet
93