82801CA Datasheet, PDF (490/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Testability
Table 18-4. XOR Chain #2 (RTCRST# Asserted for 5 PCI Clocks While PWROK Active)
Pin Name
AD8
AD7
AD14
AD12
DEVSEL#
PERR#
PLOCK#
AD27
IRDY#
AD17
C/BE2#
AD31
AD29
AD23
AD19
Ball #
Notes
L2
Top of XOR Chain
L1
2nd signal in XOR
M5
M4
M3
M2
M1
N4
N3
N2
N1
P5
P4
P3
P2
Pin Name
AD21
AD25
C/BE3#
REQ3#
LDRQ0#
LAD2/FWH2
LFRAME#
LAD3/FWH3
LAD1/FWH1
LDRQ1#
LAD0/FHW0
GPIO7
GPIO[6]
THRM#
GPIO21
TP[0]#
Ball #
P1
R1
R2
R4
T2
T3
U1
U2
U3
U4
V1
V2
V4
U5
V5
AB3
Notes
XOR Chain #2
OUTPUT
490
Intel^® 82801CA ICH3-S Datasheet