82801CA Datasheet, PDF (365/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
IDE Controller Registers (D31:F1) 10
10.1 PCI Configuration Registers (IDE—D31:F1)
Note: Registers that are not shown should be treated as Reserved (See Section 6.2 for details).
All of the IDE registers are in the core well. None can be locked.
Table 10-1. PCI Configuration Map (IDE-D31:F1)
Offset
Mnemonic
Register Name
Default
Type
00–01h
VID
Vendor ID
8086h
RO
02–03h
DID
Device ID
248Bh
RO
04–05h
CMD
Command
00h
R/W
06–07h
STS
Device Status
0280h
R/W
08h
RID
Revision ID
See Note 2
RO
09h
PI
Programming Interface
8Ah
RO
0Ah
SCC
Sub Class Code
01h
RO
0Bh
BCC
Base Class Code
01h
RO
0Dh
MLT
Master Latency Timer
00
RO
0Eh
HTYPE
Header Type
00h
RO
10–13h
PCMD_BAR Primary Command Block Base Address
00000001h
R/W
14–17h
PCNL_BAR Primary Control Block Base Address
00000001h
R/W
18–1Bh
SCMD_BAR Secondary Command Block Base Address
00000001h
R/W
1C–1Fh
SCNL_BAR Primary Command Block Base Address
00000001h
R/W
20–23h
BAR
Base Address Register
00000001h
R/W
24–27h
EXBAR
Expansion BAR
00h
R/W
2C–2Dh
SVID
Subsystem Vendor ID
00
R/Write-
Once
2E–2Fh
SID
Subsystem ID
00
R/Write-
Once
3C
INTR_LN
Interrupt Line
00
R/W
3D
INTR_PN
Interrupt Pin
01
R/W
40–41h
IDE_TIMP Primary IDE Timing
0000h
R/W
42–43h
ID_TIMS
Secondary IDE Timing
0000h
R/W
44h
SIDETIM
Slave IDE Timing
00h
R/W
48h
SDMAC
Synchronous DMA Control Register
00h
R/W
4A–4Bh
SDMATIM
Synchronous DMA Timing Register
0000h
R/W
54h
IDE_CONFIG IDE I/O Configuration Register
00h
R/W
NOTES:
1. The ICH3 IDE controller is not arbitrated as a PCI device, therefore it doe s not need a master latency timer.
2. Refer to the Specification Update for the Revision ID.
Intel^® 82801CA ICH3-S Datasheet
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