82801CA Datasheet, PDF (474/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Electrical Characteristics
Table 16-19. Power Management Timings
Sym
Parameter
Min Max Units
Notes Fig
t181
VccSus active to SLP_S3#, SLP_S5#, SUS_STAT#
and PCIRST# active
50
ns
16-20
t182 RSMRST# inactive to SUSCLK running, SLP_S3#,
t183 SLP_S5# inactive
110
ms
7
16-20
t184
Vcc active to STPCLK# and CPUSLP# inactive, and
CPU Frequency Strap signals high
50
ns
16-20
16-21
PWROK and VRMPWRGD active to SUS_STAT#
t185 inactive and processor Frequency Straps latched to 32
34 RTCCLK
1
16-20
Strap Values
t186
CPU Reset Complete to Frequency Strap signals
unlatched from Strap Values
7
9
CLK66
2
16-20
t187 STPCLK# active to Stop Grant cycle
N/A N/A
3
16-21
t188 Stop Grant cycle to CPUSLP# active
60
63 PCICLK
4
16-21
t192 CPUSLP# active to SUS_STAT# active
2
4 RTCCLK
1
16-21
t193 SUS_STAT# active to PCIRST# active
9
21 RTCCLK
1
16-21
t194 PCIRST# active to SLP_S3# active
1
t195 SLP_S3# active to SLP_S5# active
1
t196 SLP_S3# active to PWROK, VRMPWRGD inactive
0
t197
PWROK, VRMPWRGD inactive to Vcc supplies
inactive
20
2 RTCCLK
1
16-21
2 RTCCLK 1, 6 16-21
ms
5
16-21
ns
16-21
t198 Wake Event to SLP_S3#, SLP_S5# inactive
1
10 RTCCLK
1
16-21
t204
Processor I/F signals latched prior to STPCLK#
active
t205 Break Event to STPCLK# inactive
t206
STPCLK# inactive to Processor I/F signals
unlatched
0
4
CLK66
30 3120
ns
240 1880
ns
2
16-22
16-22
16-22
NOTES:
1. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 us.
2. This transition is clocked off the 66 MHz CLK66. 1 CLK66 is approximately 15 ns.
3. The ICH3 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing
for this cycle getting to the ICH3 is dependant on the processor and the memory controller.
4. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30ns.
5. The ICH3 has no maximum timing requirement for this transition. It is up to the system designer to determine
if the SLP_S3# and SLP_S5# signals are used to control the power planes.
6. If the transition to S5 is due to Power Button Override, SLP_S3# and SLP_S5# are asserted together
following timing t194 (PCIRST# active to SLP_S3# and SLP_S5# active).
7. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay
from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.
474
Intel^® 82801CA ICH3-S Datasheet