82801CA Datasheet, PDF (316/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.5
Advanced Interrupt Controller (APIC)
9.5.1 APIC Register Map
The APIC is accessed via an indirect addressing scheme. Two registers are visible by software for
manipulation of most of the APIC registers. These registers are mapped into memory space. The
registers are shown in Table 9-4.
Table 9-4. APIC Direct Registers
Address
FEC0_0000h
FEC0_0010h
FECO_0020h
FECO_0040h
Register Name
Index Register
Data Register
IRQ Pin Assertion Register
EOI Register
Size
8 bits
32 bits
8 bits
8 bits
Type
R/W
R/W
WO
WO
Table 9-5 lists the registers which can be accessed within the APIC via the Index Register. When
accessing these registers, accesses must be done a DWord at a time. For example, software should
never access byte 2 from the Data register before accessing bytes 0 and 1. The hardware will not
attempt to recover from a bad programming model in this case.
Table 9-5. APIC Indirect Registers
Index
00h
01h
02h
03h
03–0Fh
10–11h
12–13h
...
3E–3Fh
40–FFh
ID
Version
Arbitration ID
Boot Configuration
Reserved
Redirection Table 0
Redirection Table 1
...
Redirection Table 23
Reserved
Register Name
Size
32 bits
32 bits
32 bits
32 bits
64 bits
64 bits
...
64 bits
Type
R/W
RO
RO
R/W
RO
R/W
R/W
...
R/W
RO
9.5.2
.
IND—Index Register
Memory Address FEC0_0000h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
The Index Register will select which APIC indirect register to be manipulated by software. The
selector values for the indirect registers are listed in Table 9-5. Software will program this register
to select the desired APIC internal register
Bit
Description
7:0 APIC Index—R/W. This is an 8 bit pointer into the I/O APIC register table.
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Intel^® 82801CA ICH3-S Datasheet