82801CA Datasheet, PDF (51/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
2.19 Power and Ground
Table 2-19. Power and Ground Signals
Name
Description
Vcc3_3
3.3 V supply for Core well I/O buffers (15 pins). This power may be shut off in S3, S5 or
G3 states.
Vcc1_8
1.8 V supply for Core well logic (12 pins). This power may be shut off in S3, S5 or G3
states.
V5REF[2:1]
Reference for 5V tolerance on Core well inputs. This power may be shut off in S3, S5 or
G3 states.
HIREF
0.9 V reference for the hub interface. This power is shut off in S3, S5 or G3 states.
VccSus3_3
3.3 V supply for Resume well I/O buffers (8 pins). This power is not expected to be shut off
unless the system is unplugged.
VccSus1_8
1.8 V supply for Resume well logic (13 pins). This power is not expected to be shut off
unless the system is unplugged.
Reference for 5 V tolerance on Resume well inputs. This power is not expected to be shut
V5REF_Sus[2:1] ^{off unless the system is unplugged.}
NOTE: See platform design guide for V5REF_Sus connectivity.
VccRTC
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not
expected to be shut off unless the RTC battery is removed or completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull
VccRTC low. Clearing CMOS in an ICH3-based platform can be done by using a
jumper on RTCRST# or GPI, or using SAFEMODE strap.
VBIAS
RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is
mirrored throughout the oscillator and buffer circuitry. See Section 2.20.4.
V_CPU_IO
Powered by the same supply as the processor I/O voltage (3 pins). This supply is used to
drive the processor I/F outputs.
Vss
Grounds (104 pins).
Intel^® 82801CA ICH3-S Datasheet
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