82801CA Datasheet, PDF (40/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
2.4
Firmware Hub Interface
Table 2-4. Firmware Hub Interface Signals
Name
FWH[3:0] /
LAD[3:0]
FWH[4] /
LFRAME#
Type
Description
I/O Firmware Hub Signals. Muxed with LPC address signals.
I/O Firmware Hub Signals. Muxed with LPC LFRAME# signal.
2.5
PCI Interface
Table 2-5. PCI Interface Signals
Name
AD[31:0]
C/BE[3:0]#
DEVSEL#
FRAME#
Type
Description
PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the
I/O
first clock of a transaction, AD[31:0] contain a physical address (32 bits). During
subsequent clocks, AD[31:0] contain data. The ICH3 will drive all 0s on AD[31:0]
during the address phase of all PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# define the
Byte Enables.
C/BE[3:0]# Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
I/O
0110
0111
Memory Read
Memory Write
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1110
Memory Read Line
1111
Memory Write and Invalidate
All command encodings not shown are reserved. The ICH3 does not decode
reserved values, and therefore will not respond if a PCI master generates a cycle
using one of the reserved values.
Device Select: The ICH3 asserts DEVSEL# to claim a PCI transaction. As an
output, the ICH3 asserts DEVSEL# when a PCI master peripheral attempts an
access to an internal ICH3 address or an address destined for the hub interface
I/O (main memory or AGP). As an input, DEVSEL# indicates the response to an
ICH3-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading
edge of PCIRST#. DEVSEL# remains tri-stated by the ICH3 until driven by a
Target device.
Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and
duration of a PCI transaction. While the initiator asserts FRAME#, data transfers
I/O
continue. When the initiator negates FRAME#, the transaction is in the final data
phase. FRAME# is an input to the ICH3 when the ICH3 is the target, and FRAME#
is an output from the ICH3 when the ICH3 is the Initiator. FRAME# remains tri-
stated by the ICH3 until driven by an Initiator.
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Intel^® 82801CA ICH3-S Datasheet