82801CA Datasheet, PDF (257/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
The Statistical Counters are initially set to zero by the ICH3’s integrated LAN Controller after
reset. They cannot be preset to anything other than zero. The LAN Controller increments the
counters by internally reading them, incrementing them and writing them back. This process is
invisible to the processor and PCI bus. In addition, the counters adhere to the following rules:
• The counters are wrap-around counters. After reaching FFFFFFFFH the counters wrap around
to 0.
• The LAN Controller updates the required counters for each frame. It is possible for more than
one counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The LAN Controller supports all mandatory and recommend statistics functions
through the status of the receive header and directly through these Statistical Counters.
The processor can access the counters by issuing a Dump Statistical Counters SCB command. This
provides a “snapshot”, in main memory, of the internal LAN Controller statistical counters. The
LAN Controller supports 21 counters. The dump could consist of the either 16, 19, or all 21
counters, depending on the status of the Extended Statistics Counters and TCO Statistics
configuration bits in the Configuration command.
Intel^® 82801CA ICH3-S Datasheet
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