82801CA Datasheet, PDF (88/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.3.1.5 SYNC
Valid values for the SYNC field are shown in Table 5-6.
Table 5-6. SYNC Bit Definition
Bits[3:0]
Indication
0000
0101
0110
1001
1010
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request
deassertion and no more transfers desired for that channel.
Short Wait: Part indicating wait-states. For bus master cycles, the ICH3 will not use this
encoding. It will instead use the Long Wait encoding (see next encoding below).
Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding driven
by the ICH3 for bus master cycles, rather than the Short Wait (0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and more
DMA transfers desired to continue after this transfer. This value is valid only on DMA transfers
and is not allowed for any other type of cycle.
Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal
on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this
transfer. For DMA transfers, this not only indicates an error, but also indicates DMA request
deassertion and no more transfers desired for that channel.
NOTE: All other combinations are Reserved.
5.3.1.6 SYNC Time-out
There are several error cases that can occur on the LPC I/F. Table 5-7 identifies the failing cases
and the ICH3 responses.
Table 5-7. Intel^® ICH3 Response to Sync Failures
Possible Sync Failure
Intel^® ICH3 Response
ICH3 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC
after four consecutive clocks. This could occur if the processor tries to access
an I/O location to which no device is mapped.
ICH3 drives a Memory, I/O, or DMA cycle, and a peripheral drives more than
eight consecutive valid SYNC to insert wait-states using the Short (0101b)
encoding for SYNC. This could occur if the peripheral is not operating properly.
ICH3 starts a Memory, I/O, or DMA cycle, and a peripheral drives an invalid
SYNC pattern. This could occur if the peripheral is not operating properly or if
there is excessive noise on the LPC I/F.
ICH3 aborts the cycle after
the fourth clock.
Continues waiting
ICH3 aborts the cycle when
the invalid Sync is
recognized.
There may be other peripheral failure conditions; however, these are not handled by the ICH3.
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Intel^® 82801CA ICH3-S Datasheet