82801CA Datasheet, PDF (273/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.31
ERR_STS—Error Status Register (HUB-PCI—D30:F0)
Offset Address: 92h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
This register records the cause of system errors in Device 30. The actual assertion of SERR# is
enabled via the PCI Command register.
Bit
Description
7:3 Reserved.
SERR# Due to Received Target Abort (SERR_RTA)—R/W.
2
0 = This bit is cleared by writing a 1.
1 = The ICH3 sets this bit when the ICH3 receives a target abort. If SERR_EN, the ICH3 will also
generate an SERR# when SERR_RTA is set.
SERR# Due to Delayed Transaction Timeout (SERR_DTT)—R/W.
0 = This bit is cleared by writing a 1
1
1 = When a PCI master does not return for the data within 1024 clocks of the cycle’s completion,
the ICH3 clears the delayed transaction, and sets this bit. If both SERR_DTT_EN and
SERR_EN are set, then ICH3 will also generate an SERR# when SERR_DTT is set..
0 Reserved.
Intel^® 82801CA ICH3-S Datasheet
273