82801CA Datasheet, PDF (510/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Table A-3. Intel^® ICH3 Variable I/O Registers (Continued)
Register Name
Offset
Datasheet Section and Location
GPIO I/O Registers at GPIOBASE + Offset
GPIOBASE is set in Section 9.1.14, “GPIOBASE—GPIO Base Address Register (LPC I/F—D31:F0)” on
page 9-282
GPIO Use Select
GPIO Input/Output Select
GPIO Level for Input or Output
GPIO Blink Enable
GPIO Signal Invert
00–03h
04–07h
0C–0Fh
18–1Bh
2C–2Fh
Section 9.10.2, “GPIO_USE_SEL—GPIO Use Select
Register” on page 9-360
Section 9.10.3, “GP_IO_SEL—GPIO Input/Output
Select Register” on page 9-361
Section 9.10.4, “GP_LVL—GPIO Level for Input or
Output Register” on page 9-361
Section 9.10.5, “GPO_BLINK—GPO Blink Enable
Register” on page 9-362
Section 9.10.6, “GPI_INV—GPIO Signal Invert
Register” on page 9-362
BMIDE I/O Registers at BM_BASE + Offset
BM_BASE is set at Section 10.1.12, “SCMD_BAR—Secondary Command Block Base Address Register
(IDE D31:F1)” on page 10-369
Command Register Primary
Status Register Primary
Descriptor Table Pointer Primary
Command Register Secondary
Status Register Secondary
Descriptor Table Pointer Secondary
00h
02h
04–07h
08h
0Ah
0C–0Fh
Section 10.2.1, “BMIC[P,S]—Bus Master IDE
Command Register” on page 10-378
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status
Register” on page 10-379
Section 10.2.3, “BMID[P,S]—Bus Master IDE
Descriptor Table Pointer Register” on page 10-379
Section 10.2.1, “BMIC[P,S]—Bus Master IDE
Command Register” on page 10-378
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status
Register” on page 10-379
Section 10.2.3, “BMID[P,S]—Bus Master IDE
Descriptor Table Pointer Register” on page 10-379
USB I/O Registers at Base Address + Offset
USB Base Address is set at Section 11.1.10, “BASE—Base Address Register (USB—D29:F0/F1/F2)” on
page 11-385
USB Command Register
00–01h
Section 11.2.1, “USBCMD—USB Command Register”
on page 11-390
USB Status Register
USB Interrupt Enable
02–03h
04–05h
Section 11.2.2, “USBSTA—USB Status Register” on
page 11-393
Section 11.2.3, “USBINTR—Interrupt Enable
Register” on page 11-394
USB Frame Number
06–07h
Section 11.2.4, “FRNUM—Frame Number Register”
on page 11-394
USB Frame List Base Address
USB Start of Frame Modify
08–0Bh
0Ch
Section 11.2.5, “FRBASEADD—Frame List Base
Address Register” on page 11-395
Section 11.2.6, “SOFMOD—Start of Frame Modify
Register” on page 11-395
Port 0, 2 Status/Control
10–11h
Section 11.2.7, “PORTSC[0,1]—Port Status and
Control Register” on page 11-396
Port 1, 3 Status/Control
Loop Back Test Data
12–13h
18h
Section 11.2.7, “PORTSC[0,1]—Port Status and
Control Register” on page 11-396
510
Intel^® 82801CA ICH3-S Datasheet