82801CA Datasheet, PDF (350/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.15
DEVTRAP_EN— Device Trap Enable Register
I/O Address:
Default Value
Lockable:
Power Well:
PMBASE +48h
0000h
No
Core
Attribute:
Size:
Usage:
R/W
16-bit
Legacy Only
This register enables the individual trap ranges to generate an SMI# when the corresponding status
bit in the DEVACT_STS register is set. When a range is enabled, I/O cycles associated with that
range will not be forwarded to LPC or IDE.
Bit
Description
15:14
13
12
11
10
9:6
5
4
3
2
1
0
Reserved.
ADLIB_TRP_EN—R/W. Ad-Lib.
0 = Disable.
1 = Enable.
KBC_TRP_EN—R/W. KBC (60/64h).
0 = Disable.
1 = Enable.
MIDI_TRP_EN—R/W. MIDI.
0 = Disable.
1 = Enable.
AUDIO_TRP_EN—R/W. Audio (Sound Blaster “OR’d” with MSS).
0 = Disable.
1 = Enable.
Reserved.
LEG_IO_TRP_EN—R/W. Parallel Port, Serial Port 1, Serial Port 2, Floppy Disk Controller.
0 = Disable.
1 = Enable.
Reserved.
IDES1_TRP_EN—R/W. IDE Secondary Drive 1.
0 = Disable.
1 = Enable.
IDES0_TRP_EN—R/W. IDE Secondary Drive 0.
0 = Disable.
1 = Enable.
IDEP1_TRP_EN—R/W. IDE Primary Drive 1.
0 = Disable.
1 = Enable.
IDEP0_TRP_EN—R/W. IDE Primary Drive 0.
0 = Disable.
1 = Enable.
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Intel^® 82801CA ICH3-S Datasheet