82801CA Datasheet, PDF (491/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Testability
Table 18-5. XOR Chain #3 (RTCRST# asserted for 6 PCI Clocks While PWROK Active)
Pin Name
PDD10
PDD5
PDD7
PDD6
PDD8
PDD9
PDD2
PDD12
PDD3
PDD4
PDD11
PDD14
PDD1
PDD13
PDD0
PDIOW#
PDDREQ
PDD15
PDDACK#
PIORDY
PDIOR#
PDA0
IRQ14
PDA1
PDA2
PDCS3#
PDCS1#
IRQ15
Ball #
Notes
W9
Top of XOR Chain
Y9
2nd signal in XOR
AA9
AB9
AC9
Y10
AA10
AB10
AC10
W11
Y11
AA11
AB11
AC11
W12
Y12
AB12
AC12
Y13
AB13
AC13
AA14
AB14
AC14
AA15
AB15
AC15
W19
Pin name
GPIO[19]
GPIO[20]
VRMPWRGD
GPIO[22]
GPIO[18]
GPIO[23]
A20GATE
RCIN#
CPUPWRGD
NC
NC
INIT#
SMI#
CPU_SLP#
IGNNE#
NMI
INTR
A20M#
STPCLK#
HI_STBF
GPIO32
GPIO35
GPIO33
GPIO34
GPIO37
GPIO36
RI#
Ball #
Notes
W20
V21
V19
Y20
U21
U20
Y22
U22
W23
AB21
AB22
AB23
Y23
W21
AA21
Y21
AA23
V23
U23
P23
H20
G19
G22
F21
E21
E22
Last in XOR Chain
XOR Chain #3
AA1
OUTPUT
Intel^® 82801CA ICH3-S Datasheet
491