82801CA Datasheet, PDF (121/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.8.4
5.8.4.1
5.8.4.2
PCI Message-Based Interrupts
Theory of Operation
The following scheme is only supported when the internal I/O(x) APIC is used (rather than just the
8259). The ICH3 supports the new method for PCI devices to deliver interrupts as write cycles,
rather than using the traditional PIRQ[A:D] signals. Essentially, the PCI devices are given a write
path directly to a register that will cause the desired interrupt. This mode is only supported when
the ICH3’s internal I/O APIC is enabled. Upon recognizing the write from the peripheral, the ICH3
will send the interrupt message to the processor using the I/O APIC’s serial bus.
The interrupts associated with the PCI Message-based interrupt method must be set up for edge
triggered mode, rather than level triggered, since the peripheral only does the write to indicate the
edge.
The following sequence is used:
1. During PCI PnP, the PCI peripheral is first programmed with an address
(MESSAGE_ADDRESS) and data value (MESSAGE_DATA) that will be used for the
interrupt message delivery. For the ICH3, the MESSAGE_ADDRESS is the IRQ Pin assertion
register, which is mapped to memory location: FEC0_0020h.
2. To cause the interrupt, the PCI peripheral requests the PCI bus and when granted, writes the
MESSAGE_DATA value to the location indicated by the MESSAGE_ADDRESS. The
MESSAGE_DATA value indicates which interrupt occurred. This MESSAGE_DATA value is
a binary encoded. For example, to indicate that interrupt 7 should go active, the peripheral will
write a binary value of 0000111. The MESSAGE_DATA will be a 32-bit value, although only
the lower 5 bits are used.
3. If the PRQ bit in the APIC Version Register is set, the ICH3 positively decodes the cycles (as a
slave) in Medium time.
4. The ICH3 decodes the binary value written to MESSAGE_ADDRESS and sets the appropriate
IRR bit in the internal I/O APIC. The corresponding interrupt must be set up for edge-
triggered interrupts. The ICH3 supports interrupts 00h through 23h. Binary values outside this
range will not cause any action.
5. After sending the interrupt message to the processor, the ICH3 will automatically clear the
interrupt.
Because they are edge triggered, the interrupts that are allocated to the PCI bus for this scheme may
not be shared with any other interrupt (e.g., the standard PCI PIRQ[A:D], those received via
SERIRQ#, or the internal level-triggered interrupts such as SCI or TCO).
The ICH3 ignores interrupt messages sent by PCI masters that attempt to use IRQ0, 2, 8, or 13.
Registers and Bits Associated with PCI Interrupt Delivery
Capabilities Indication
The capability to support PCI interrupt delivery will be indicated via ACPI configuration
techniques. This involves the BIOS creating a data structure that gets reported to the ACPI
configuration software. The OS reads the PRQ bit in the APIC Version Register to see if the ICH3
is capable of support PCI-based interrupt messages. As a precaution, the PRQ bit will not be set if
the XAPIC_EN bit is not set.
Interrupt Message Register
The PCI devices will all write their message into the IRQ pin assertion register, which is a
memory-mapped register located at the APIC base memory location + 20h.
Intel^® 82801CA ICH3-S Datasheet
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