82801CA Datasheet, PDF (410/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

SMBus Controller Registers (D31:F3)
12.2.13 SLV_STS—Slave Status Register
Register Offset: 10h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll
this register until a write takes effect before assuming that a write has completed internally.
Bit
Description
7:1 Reserved.
HOST_NOTIFY_STS—R/WC. The ICH3 sets this bit to a 1 when it has completely received a
successful Host Notify Command on the SMLink pins. Software reads this bit to determine that the
source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this bit
0 after reading any information needed from the Notify address and data registers by writing a 1 to this
bit. Note that the ICH3 will allow the Notify Address and Data registers to be over-written once this bit
has been cleared. When this bit is 1, the ICH3 will NACK the first byte (host address) of any new “Host
Notify” commands on the SMLink. Writing a 0 to this bit has no effect.
12.2.14 SLV_CMD—Slave Command Register
Register Offset: 11h
Default Value: 00h
Attribute:
Size:
Note: This register is in the resume well and is reset by RSMRST#
R/W
8 bits
Bit
Description
7:2 Reserved.
SMBALERT_DIS—R/W.
0 = Allows the generation of the interrupt or SMI#.
2 ^{1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT#}
source. This bit is logically inverted and ANDed with the SMBALERT_STS bit. The resulting
signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the
wake logic.
HOST_NOTIFY_WKEN—R/W. Software sets this bit to 1 to enable the reception of a Host Notify
1 command as a wake event. When enabled this event is “OR”ed in with the other SMBus wake events
and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register.
HOST_NOTIFY_INTREN—R/W. Software sets this bit to 1 to enable the generation of interrupt or
SMI# when HOST_NOTIFY_STS is 1. This enable does not affect the setting of the
0
HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQ[B]# or SMI# is generated,
depending on the value of the SMB_SMI_EN bit (D31, F3, Off40h, B1). If the HOST_NOTIFY_STS bit
is set when this bit is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or
SMI#) is logically generated by ANDing the STS and INTREN bits.
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Intel^® 82801CA ICH3-S Datasheet