82801CA Datasheet, PDF (76/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
accesses to the control structure, the LAN Controller uses the Memory Write (MW) command. For
write accesses to data structure, the LAN Controller may use either the Memory Write or Memory
Write and Invalidate (MWI) commands.
Read Accesses: The LAN Controller performs block transfers from host system memory in order
to perform frame transmission on the serial link. In this case, the LAN Controller initiates zero
wait-state memory read burst cycles for these accesses. The length of a burst is bounded by the
system and the LAN Controller’s internal FIFO. The length of a read burst may also be bounded by
the value of the Transmit DMA Maximum Byte Count in the Configure command. The Transmit
DMA Maximum Byte Count value indicates the maximum number of transmit DMA PCI cycles
that will be completed after an LAN Controller internal arbitration.
The LAN Controller, as the initiator, drives the address lines AD[31:0], the command and byte
enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The LAN Controller asserts
IRDY# to support zero wait-state burst cycles. The target signals the LAN Controller that valid
data is ready to be read by asserting the TRDY# signal.
Write Accesses: The LAN Controller performs block transfers to host system memory during
frame reception. In this case, the LAN Controller initiates memory write burst cycles to deposit the
data, usually without wait-states. The length of a burst is bounded by the system and the LAN
Controller’s internal FIFO threshold. The length of a write burst may also be bounded by the value
of the Receive DMA Maximum Byte Count in the Configure command. The Receive DMA
Maximum Byte Count value indicates the maximum number of receive DMA PCI transfers that
will be completed before the LAN Controller internal arbitration.
The LAN Controller, as the initiator, drives the address lines AD[31:0], the command and byte
enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The LAN Controller asserts
IRDY# to support zero wait-state burst cycles. The LAN Controller also drives valid data on
AD[31:0] lines during each data phase (from the first clock and on). The target controls the length
and signals completion of a data phase by deassertion and assertion of TRDY#.
• Cycle Completion: The LAN Controller completes (terminates) its initiated memory burst
cycles in the following cases:
• Normal Completion: All transaction data has been transferred to or from the target device
(for example, host main memory).
• Backoff: Latency Timer has expired and the bus grant signal (GNT#) was removed from the
LAN Controller by the arbiter, indicating that the LAN Controller has been preempted by
another bus master.
• Transmit or Receive DMA Maximum Byte Count: The LAN Controller burst has reached
the length specified in the Transmit or Receive DMA Maximum Byte Count field in the
Configure command block.
• Target Termination: The target may request to terminate the transaction with a target-
disconnect, target-retry, or target-abort. In the first two cases, the LAN Controller initiates the
cycle again. In the case of a target-abort, the LAN Controller sets the received target-abort bit
in the PCI Configuration Status field (PCI configuration status register, bit 12) and does not re-
initiate the cycle.
• Master Abort: The target of the transaction has not responded to the address initiated by the
LAN Controller (in other words, DEVSEL# has not been asserted). The LAN Controller
simply deasserts FRAME# and IRDY# as in the case of normal completion.
• Error Condition: In the event of parity or any other system error detection, the LAN
Controller completes its current initiated transaction. Any further action taken by the LAN
Controller depends on the type of error and other conditions.
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Intel^® 82801CA ICH3-S Datasheet