82801CA Datasheet, PDF (58/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Power Planes and Pin States
Table 3-4. Power Plane and States for Output and I/O Signal (Continued)
Signal Name
Power
Plane
During
PCIRST#⁴ /
RSMRST#⁵
Immediately
after
PCIRST#⁴ /
RSMRST#⁵
S1
LAN Connect and EEPROM Interface
EE_CS
EE_DOUT
EE_SHCLK
LAN_RSTSYNC
LAN_TXD[2:0]
Resume I/O
Resume I/O
Resume I/O
Resume I/O
Resume I/O
Low
High
Low
High
Low
Running
High
Running
Defined
Defined
Defined
Defined
Defined
Defined
Defined
IDE Interface
PDA[2:0], SDA[2:0]
PDCS1#, PDCS3#
PDD[15:8], SDD[15:8],
PDD[6:0], SDD[6:0]
PDD[7], SDD[7]
PDDACK#, SDDACK#
PDIOR#, PDIOW#
SDCS1#, SDCS3#
SDIOR#, SDIOW#
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Undefined
High
High-Z
Low
High
High
High
High
Undefined
High
High-Z
Low
High
High
High
High
Undefined
High
High-Z
Low
High
High
High
High
Interrupts
PIRQ[A:H]#
SERIRQ
APICD[1:0]
Main I/O
Main I/O
Main I/O
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
USB Interface
USBP[5:0][P,N]
Resume I/O
Low
Low
Low
Power Management
SLP_S3#
SLP_S5#
SUS_STAT#
SUSCLK
Resume I/O
Low
Resume I/O
Low
Resume I/O
Low
Resume I/O
Low
High
High
High
after
PWROK
rises
High
High
High
Running
S3
Defined
Defined
Defined
Defined
Defined
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Low
Low
High
Low
S4/S5
Defined
Defined
Defined
Defined
Defined
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Low
Low
Low
Low
3-58
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