82801CA Datasheet, PDF (284/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.1.18
9.1.19
.
PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
PIRQE–68h, PIRQF–69h,
PIRQG–6Ah, PIRQH–6Bh
80h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
Interrupt Routing Enable (IRQEN)—R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
7
NOTE: BIOS must program this bit to “0” during POST for any of the PIRQs that are being used.
The value of this bit may subsequently be changed by the OS when setting up for I/O APIC
interrupt delivery mode.
6:4 Reserved.
IRQ Routing—R/W (ISA compatible).
0000 = Reserved
0001 = Reserved
3:0 ^{0010 = Reserved}
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = IRQ6
0111 = IRQ7
1000 = Reserved
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = IRQ12
1101 = Reserved
1110 = IRQ14
1111 = IRQ15
D31_ERR_CFG—Device 31 Error Configuration Register
(LPC I/F—D31:F0)
Offset Address: 88h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
This register configures the ICH3’s Device 31 responses to various system errors. The actual
assertion of SERR# is enabled via the PCI Command register
Bit
Description
7:3 Reserved.
SERR# on Received Target Abort Enable (SERR_RTA_EN)—R/W.
2 _{0 = Disable. No SERR# assertion on Received Target Abort.}
1 = The ICH3 will generate SERR# when SERR_RTA is set if SERR_EN is set.
SERR# on Delayed Transaction Timeout Enable (SERR_DTT_EN)—R/W.
1 _{0 = Disable. No SERR# assertion on Delayed Transaction Timeout.}
1 = The ICH3 will generate SERR# when SERR_DTT bit is set if SERR_EN is set.
0 Reserved.
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Intel^® 82801CA ICH3-S Datasheet