82801CA Datasheet, PDF (470/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Electrical Characteristics
Table 16-11. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Continued)
Sym
Parameter¹
Mode 3
(ns)
Min Max
Mode 4
(ns)
Min Max
Mode 5
(ns)
Min Max
Measuring
Location
t98a
Maximum time before releasing
IORDY (Tiordyz)
20
20
20
Device
Connector
t98b
Minimum time before driving
IORDY ² (Tziordy)
0
0
0
Device
Connector
Time from STROBE edge to
t99
negation of DMARQ or assertion
of STOP (when sender terminates
50
50
50
Sender
Connector
a burst) (Tss)
Recipient IC data setup time (from
t83b data valid until STROBE edge)²
6.8
4.8
2.3
ICH3 Balls
(Tdsic)
Recipient IC data hold time (from
t84b STROBE edge until data may
4.8
4.8
2.8
ICH3 Balls
become invalid)² (Tdhic)
Sender IC data valid setup time
t85b (from data valid until STROBE
22.6
9.5
6.0
ICH3 Balls
edge)² (Tdvsic)
Sender IC data valid hold time
t86b (from STROBE edge until data
9.0
9.0
6.0
ICH3 Balls
may become invalid)² (Tdvhic)
Figure
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface
(ATA/ATAPI - 6) specification name.
2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on measuring
these timing parameters.
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Intel^® 82801CA ICH3-S Datasheet