82801CA Datasheet, PDF (94/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.4.4
5.4.5
5.4.5.1
5.4.5.2
5.4.5.3
Autoinitialize
By programming a bit in the DMA channel mode register, a channel may be set up as an
autoinitialize channel. When a channel undergoes autoinitialization, the original values of the
current page, current address and current byte/word count registers are automatically restored from
the base page, address, and byte/word count registers of that channel following TC. The base
registers are loaded simultaneously with the current registers by the microprocessor when the
DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is
not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to
perform another DMA service, without processor intervention, as soon as a valid DREQ is
detected.
Software Commands
There are three additional special software commands that the DMA controller can execute. The
three software commands are:
1. Clear Byte Pointer Flip-Flop
2. Master Clear
3. Clear Mask Register
They do not depend on any specific bit pattern on the data bus.
Clear Byte Pointer Flip-Flop
This command is executed prior to writing or reading new address or word count information to/
from the DMA controller. This initializes the flip-flop to a known state so that subsequent accesses
to register contents by the microprocessor will address upper and lower bytes in the correct
sequence.
When the host processor is reading or writing DMA registers, two byte pointer flip-flops are used;
one for channels 0–3 and one for channels 4–7. Both of these act independently. There are separate
software commands for clearing each of them (0Ch for channels 0–3, 0D8h for channels 4–7).
DMA Master Clear
This software instruction has the same effect as the hardware reset. The command, status, request,
and internal first/last flip-flop registers are cleared and the mask register is set. The DMA
controller will enter the idle cycle.
There are two independent master clear commands; 0Dh which acts on channels 0–3, and 0DAh
which acts on channels 4–7.
Clear Mask Register
This command clears the mask bits of all four channels, enabling them to accept DMA requests.
I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7.
94
Intel^® 82801CA ICH3-S Datasheet