82801CA Datasheet, PDF (72/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.2.2 LAN Controller Architectural Overview
Figure 5-4 is a high level block diagram of the ICH3 integrated LAN Controller. It is divided into
four main subsystems: a Parallel subsystem, a FIFO subsystem and the Carrier-Sense Multiple
Access with Collision Detect (CSMA/CD) unit.
Figure 5-4. Integrated LAN Controller Block Diagram
EEPROM
Interface
PCI
Interface
PCI Target and
EEPROM
Interface
3 KB
Tx FIFO
Four Channel
Addressing Unit - DMA
PCI Bus Interface Unit
(BIU)
M icro -m achine
Data Interface Unit
(DIU)
Dual Ported
FIFO
FIFO Control
3 KB
Rx FIFO
CSMA/CD Unit
LAN
Connect
Interface
5.2.2.1
Parallel Subsystem
The parallel subsystem is broken down into several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
EEPROM/ interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data
(such as transmit, receive, and configuration data) and command and status parameters between
these two blocks.
The PCI bus master interface provides a complete interface to the PCI bus and is compliant with
the PCI Local Bus Specification, Revision 2.2. The LAN Controller provides 32 bits of addressing
and data, as well as the complete control interface to operate on the PCI bus. As a PCI target, it
follows the PCI configuration format which allows all accesses to the LAN Controller to be
automatically mapped into free memory and I/O space upon initialization of a PCI system. For
processing of transmit and receive frames, the integrated LAN Controller operates as a master on
the PCI bus, initiating zero wait-state transfers for accessing these data parameters.
The LAN Controller Control/Status Register Block is part of the PCI target element. The Control/
Status Register block consists of the following LAN Controller internal control registers: System
Control Block (SCB), PORT, EEPROM Control and Management Data Interface (MDI) Control.
The micromachine is an embedded processing unit contained in the LAN Controller that enables
Adaptive Technology. The micromachine accesses the LAN Controller’s microcode ROM,
working its way through the opcodes (or instructions) contained in the ROM to perform its
functions. Parameters accessed from memory, such as pointers to data buffers, are also used by the
micromachine during the processing of transmit or receive frames by the LAN Controller. A
typical micromachine function is to transfer a data buffer pointer field to the LAN Controller’s
DMA unit for direct access to the data buffer. The micromachine is divided into two units, Receive
Unit and Command Unit which includes transmit functions. These two units operate independently
and concurrently. Control is switched between the two units according to the microcode instruction
72
Intel^® 82801CA ICH3-S Datasheet