82801CA Datasheet, PDF (299/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
Table 9-2. DMA Registers (Continued)
Port
D0h
D4h
D6h
D8h
DAh
DCh
DEh
Alias
D1h
D5h
D7h
D9h
DBh
DDh
DFh
Register Name
Channel 4–7 DMA Command
Channel 4–7 DMA Status
Channel 4–7 DMA Write Single Mask
Channel 4–7 DMA Channel Mode
Channel 4–7 DMA Clear Byte Pointer
Channel 4–7 DMA Master Clear
Channel 4–7 DMA Clear Mask
Channel 4–7 DMA Write All Mask
Default
Undefined
Undefined
000001XXb
000000XXb
Undefined
Undefined
Undefined
0Fh
Type
WO
RO
WO
WO
WO
WO
WO
R/W
9.2.1
DMABASE_CA—DMA Base and Current Address Registers
I/O Address:
Default Value:
Ch. #0 = 00h; Ch. #1 = 02h
Ch. #2 = 04h; Ch. #3 = 06h
Ch. #5 = C4h Ch. #6 = C8h
Ch. #7 = CCh;
Undef
Attribute:
Size:
Lockable:
No
Power Well:
RO
16-bit (per channel),
but accessed in two 8-bit
quantities
Core
Bit
Description
Base and Current Address—R/W. This register determines the address for the transfers to be
performed. The address specified points to two separate registers. On writes, the value is stored in
the Base Address register and copied to the Current Address register. On reads, the value is returned
from the Current Address register.
The address increments/decrements in the Current Address register after each transfer, depending
on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will
15:0 _{be reloaded from the Base Address register after a terminal count is generated.}
For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit location. Bit 15
will be shifted out. Therefore, if bit 15 was a 1, it will be lost.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop.
Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the
low byte is accessed first.
Intel^® 82801CA ICH3-S Datasheet
299