82801CA Datasheet, PDF (194/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.17
5.17.1
SMBus 2.0 Controller Functional Description
(D31:F3)
The ICH3 provides a System Management Bus (SMBus) Specification, Version 2.0-compliant Host
Controller as well as an SMBus Slave Interface. The Host Controller provides a mechanism for the
processor to initiate communications with SMBus peripherals (slaves). The ICH3 is also capable of
operating in a mode in which it can communicate with I²C* compatible devices.
The ICH3 can perform SMBus messages with either packet error checking (PEC) enabled or
disabled. The actual PEC calculation and checking is performed in software.
The Slave Interface allows an external master to read from or write to the ICH3. Write cycles can
be used to cause certain events or pass messages, and the read cycles can be used to determine the
state of various status bits. The ICH3’s internal Host Controller cannot access the ICH3’s internal
Slave Interface.
The ICH3 SMBus logic exists in Device 31:Function 3 configuration space, and consists of a
transmit data path, and host controller. The transmit data path provides the data flow logic needed
to implement the seven different SMBus command protocols and is controlled by the host
controller. The ICH3 SMBus controller logic is clocked by RTC clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller
commands through software, except for the new Host Notify command (which is actually a
received message).
The programming model of the host controller is combined into two portions: a PCI configuration
portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is
done via the PCI configuration space. Real-time programming of the Host interface is done in
system I/O space.
Host Controller
The SMBus Host Controller is used to send commands to other SMBus slave devices. Software
sets up the host controller with an address, command, and, for writes, data and optional PEC; and
then tells the controller to start. When the controller has finished transmitting data on writes, or
receiving data on reads, it will generate an SMI# or interrupt, if enabled.
The host controller supports 8 command protocols of the SMBus interface (see System
Management Bus Specifications): Quick Command, Send Byte, Receive Byte, Write Byte/Word,
Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
The SMBus Host Controller requires that the various data and command fields be setup for the type
of command to be sent. When software sets the START bit, the SMBus Host Controller will
perform the requested transaction, and interrupt the processor (or generate an SMI#) when the
transaction is completed. Once a START command has been issued, the values of the “active
registers” (i.e., host control, host command, transmit slave address, data 0, data 1) should not be
changed or read until the interrupt status bit (INTR) has been set (indicating the completion of the
command). Any register values needed for computation purposes should be saved prior to issuing
of a new command, as the SMBus Host Controller will update all registers while completing the
new command.
Using the SMB Host Controller to send commands to the ICH3's SMB slave port is supported.
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Intel^® 82801CA ICH3-S Datasheet