82801CA Datasheet, PDF (332/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.1.3
9.8.1.4
GEN_PMCON_3—General PM Configuration 3 Register (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
A4h
00h
No
RTC
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
Bit
Description
7:3 Reserved.
RTC Power Status (RTC_PWR_STS)—R/WC.
0 = Software clears this bit by writing a 0 to the bit position.
1 = Indicates that the RTC battery was removed or has 0 volts. This bit is set when the RTCRST#
2
signal is low.
NOTE: Clearing CMOS in an Intel ICH3-based platform can be done by using a jumper on
RTCRST# or GPI, or using a SAFEMODE strap. Implementations should not attempt to
clear CMOS by using a jumper to pull VccRTC low.
Power Failure (PWR_FLR)—R/WC. This bit is in the RTC well, and is not cleared by any type of
reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software
1
clears this bit by writing a 1 to the bit position.
1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed.
NOTE: Clearing CMOS in an ICH3-based platform can be done by using a jumper on RTCRST# or
GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by
using a jumper to pull VccRTC low.
AFTERG3_EN—R/W. Determines what state to go to when power is re-applied after a power failure
(G3 state). This bit is in the RTC well and is not cleared by any type of reset except writes to CF9h or
RTCRST#.
0 _{0 = System will return to S0 state (boot) after power is re-applied.}
1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the
S5 state, the only enabled wake event is the Power Button or any enabled wake event that was
preserved through the power failure.
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock
period may not be detected by the ICH3.
STPCLK_DEL—Stop Clock Delay Register (PM—D31:F0)
Offset Address:
Default Value:
Power Well:
A8h
0Dh
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
Bit
Description
7:6 Reserved.
STPCLK_DEL. Selects the value for t190 (CPUSLP# inactive to STPCLK# inactive). The default
value of 0Dh yields a default of approximately 50.045 microseconds. The maximum value of 3Fh will
result in a time of 245 microseconds.
5:0 _{NOTE: Software must program the value to a range that can be tolerated by the associated}
processor and chipset. The ICH3 requires that software does not program a value of 00h or
01h; a minimum programming of 02h yields the minimum possible delay of 3.87
microseconds.
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Intel^® 82801CA ICH3-S Datasheet