82801CA Datasheet, PDF (508/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Table A-3. Intel^® ICH3 Variable I/O Registers
Register Name
Offset
Datasheet Section and Location
LAN Control/Status Registers (CSR) may be mapped to either I/O space or memory space.
LAN CSR at CSR_IO_BASE + Offset or CSR_MEM_BASE + Offset. CSR_MEM_BASE set in
Section 7.1.11, “CSR_MEM_BASE CSR—Memory-Mapped Base Address Register (LAN Controller—
B1:D8:F0)” on page 7-239 CSR_IO_BASE set in Section 7.1.12, “CSR_IO_BASE—CSR I/O-Mapped
Base Address Register (LAN Controller—B1:D8:F0)” on page 7-239
SCB Status Word
SCB Command Word
SCB General Pointer
PORT
EEPROM Control Register
MDI Control Register
Receive DMA Byte Count
Early Receive Interrupt
Flow Control Register
PMDR
General Control
General Status
01–00h
03–02h
07–04h
OB–08h
0F–0Eh
13–10h
17–14h
18h
1A–19h
1Bh
1Ch
1Dh
Section 7.2.1, “System Control Block Status Word
Register” on page 7-246
Section 7.2.2, “System Control Block Command Word
Register” on page 7-247
Section 7.2.3, “System Control Block General Pointer
Register” on page 7-249
Section 7.2.4, “PORT” on page 7-249
Section 7.2.5, “EEPROM Control Register” on
page 7-250
Section 7.2.6, “Management Data Interface (MDI)
Control Register” on page 7-251
Section 7.2.7, “Receive DMA Byte Count Register” on
page 7-251
Section 7.2.8, “Early Receive Interrupt Register” on
page 7-252
Section 7.2.9, “Flow Control Register” on page 7-253
Section 7.2.10, “Power Management Driver (PMDR)
Register” on page 7-254
Section 7.2.11, “General Control Register” on
page 7-254
Section 7.2.12, “General Status Register” on
page 7-255
Power Management I/O Registers at PMBASE+Offset
PMBASE set in Section 9.1.10, “PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)” on
page 9-280
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Processor Control
Level 2 Register
General Purpose Event 0 Status
General Purpose Event 0 Enables
00–01h
02–03h
04–07h
08–0Bh
10–13h
14h
28–29h
2A–2Bh
Section 9.8.3.1, “PM1_STS—Power Management 1
Status Register” on page 9-337
Section 9.8.3.2, “PM1_EN—Power Management 1
Enable Register” on page 9-339
Section 9.8.3.3, “PM1_CNT—Power Management 1
Control Register” on page 9-340
Section 9.8.3.4, “PM1_TMR—Power Management 1
Timer Register” on page 9-340
Section 9.8.3.5, “PROC_CNT—Processor Control
Register” on page 9-341
Section 9.8.3.6, “LV2—Level 2 Register” on
page 9-342
Section 9.8.3.7, “GPE0_STS—General Purpose
Event 0 Status Register” on page 9-342
Section 9.8.3.8, “GPE0_EN—General Purpose Event
0 Enables Register” on page 9-344
508
Intel^® 82801CA ICH3-S Datasheet