82801CA Datasheet, PDF (85/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.3
LPC Bridge (w/ System and Management Functions)
(D31:F0)
The LPC Bridge function of the ICH3 resides in PCI Device 31:Function 0. In addition to the LPC
bridge function, D31:F0 contains other functional units including DMA, Interrupt Controllers,
Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and
functions associated with other functional units (power management, GPIO, USB, IDE, etc.) are
described in their respective Sections.
5.3.1 LPC Interface
The ICH3 implements an LPC I/F as described in the Low Pin Count (LPC) Interface
Specification, Revision 1.0. The LPC I/F to the ICH3 is shown in Figure 5-6. Note that the ICH3
implements all of the signals that are shown as optional, but peripherals are not required to do so.
Figure 5-6. LPC Interface Diagram
Intel^® ICH3
PCI Bus
LA D [3 :0 ]
LFRAME#
LDRQ#
(optional)
LPCPD#
(optional)
L S M I#
(optional)
PCI
CLK
PCI
RST#
PCI
SERIRQ
PCI
PME#
Super I/O
Intel^® 82801CA ICH3-S Datasheet
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