82801CA Datasheet, PDF (195/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
The ICH3 supports slave functionality, including the Host Notify protocol, on the SMLink pins.
Therefore, in order to be fully compliant with the System Management Bus (SMBus) Specification,
Version 2.0 (which requires the Host Notify protocol), the SMLink and SMBus signals should be
tied together externally.
5.17.1.1
Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to determine the
progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the
command completes successfully, the INTR bit will be set in the Host Status Register. If the device
does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set. If
software sets the KILL bit in the Host Control Register while the command is running, the
transaction will stop and the FAILED bit will be set.
Quick Command
When programmed for a Quick command, the Transmit Slave Address Register is sent. The PEC
byte is never appended to the Quick protocol. Software should force the PEC_EN bit to 0 when
performing the Quick command. The Quick command with I2C_EN set produces undefined
results. Software should force the I2C_EN bit to 0 when performing the Quick command. The
format of the protocol is shown in Table 5-77.
Table 5-77. Quick Protocol
Bit
Description
1
Start Condition
2–8 Slave Address–7 bits
9
Read / Write Direction
10 Acknowledge from slave
11 Stop
Intel^® 82801CA ICH3-S Datasheet
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