82801CA Datasheet, PDF (10/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

5.15.5 Ultra ATA/100 Protocol ................................................................... 171
5.15.6 Ultra ATA/33/66/100 Timing ........................................................... 171
5.16 USB 1.1 Controllers (D29:F0, F1 and F2) ................................................... 172
5.16.1 Data Structures in Main Memory .................................................... 172
5.16.1.1 Frame List Pointer ........................................................... 172
5.16.1.2 Transfer Descriptor (TD) ................................................. 173
5.16.1.3 Queue Head (QH) ........................................................... 177
5.16.2 Data Transfers to/from Main Memory ............................................. 178
5.16.2.1 Executing the Schedule................................................... 178
5.16.2.2 Processing Transfer Descriptors ..................................... 179
5.16.2.3 Command Register, Status Register, and TD Status
Bit Interaction .................................................................. 180
5.16.2.4 Transfer Queuing ............................................................ 181
5.16.3 Data Encoding and Bit Stuffing....................................................... 184
5.16.4 Bus Protocol ................................................................................... 184
5.16.4.1 Bit Ordering ..................................................................... 184
5.16.4.2 SYNC Field...................................................................... 184
5.16.4.3 Packet Field Formats ...................................................... 185
5.16.4.4 Address Fields................................................................. 186
5.16.4.5 Frame Number Field ....................................................... 186
5.16.4.6 Data Field ........................................................................ 186
5.16.4.7 Cyclic Redundancy Check (CRC) ................................... 186
5.16.5 Packet Formats............................................................................... 187
5.16.5.1 Token Packets................................................................. 187
5.16.5.2 Start of Frame Packets.................................................... 187
5.16.5.3 Data Packets ................................................................... 188
5.16.5.4 Handshake Packets ........................................................ 188
5.16.5.5 Handshake Responses ................................................... 188
5.16.6 USB Interrupts ................................................................................ 189
5.16.6.1 Transaction Based Interrupts .......................................... 189
5.16.6.2 Non-Transaction Based Interrupts .................................. 191
5.16.7 USB Power Management ............................................................... 191
5.16.8 USB Legacy Keyboard Operation................................................... 192
5.17 SMBus 2.0 Controller Functional Description (D31:F3) ............................... 194
5.17.1 Host Controller ................................................................................ 194
5.17.1.1 Command Protocols........................................................ 195
5.17.1.2 I²C Behavior .................................................................... 203
5.17.1.3 Heartbeat for Use with the External LAN Controller........ 203
5.17.2 Bus Arbitration ................................................................................ 204
5.17.3 Bus Timing...................................................................................... 204
5.17.3.1 Clock Stretching .............................................................. 204
5.17.3.2 Bus Time Out (Intel^® ICH3 as SMBus Master)................ 204
5.17.4 Interrupts / SMI# ............................................................................. 205
5.17.5 SMBALERT# .................................................................................. 206
5.17.6 SMBus Slave Interface ................................................................... 206
5.17.6.1 Format of Slave Write Cycle............................................ 207
5.17.6.2 Format of Read Command.............................................. 209
5.17.6.3 Format of Host Notify Command..................................... 211
5.18 AC ’97 Controller Functional Description (Audio D31:F5, Modem D31:F6). 212
5.18.1 AC-Link ........................................................................................... 214
5.18.1.1 AC-Link Output Frame (SDOUT) .................................... 216
5.18.1.2 Output Slot 0: Tag Phase ................................................ 216
5.18.1.3 Output Slot 1: Command Address Port ........................... 217
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Intel^® 82801CA ICH3-S Datasheet