82801CA Datasheet, PDF (497/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Table A-1. Intel^® ICH3 PCI Configuration Registers (Continued)
Register Name
Memory Limit
Prefetchable Memory Base
Prefetchable Memory Limit
I/O Base Upper 16 Bits
I/O Limit Upper 16 Bits
Interrupt Line
Bridge Control
ICH3 Configuration Register
Multi-Transaction Timer
PCI Master Status
Error Command Register
Error Status Register
Vendor ID
Device ID
PCI Command Register
PCI Device Status Register
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Header Type
ACPI Base Address Register
Offset
Datasheet Section and Location
22–23h
24–25h
26–27h
30–31h
32–33h
3Ch
3E–3Fh
50–51h
70h
82h
90h
92h
Section 8.1.18, “MEMLIM—Memory Limit Register
(HUB-PCI—D30:F0)” on page 8-267
Section 8.1.19, “PREF_MEM_BASE—Prefetchable
Memory Base Register (HUB-PCI—D30:F0)” on
page 8-267
Section 8.1.20, “PREF_MEM_MLT—Prefetchable
Memory Limit Register (HUB-PCI—D30:F0)” on
page 8-268
Section 8.1.21, “IOBASE_HI—I/O Base Upper 16 Bits
Register (HUB-PCI—D30:F0)” on page 8-268
Section 8.1.22, “IOLIM_HI—I/O Limit Upper 16 Bits
Register (HUB-PCI—D30:F0)” on page 8-268
Section 8.1.23, “INT_LINE—Interrupt Line Register
(HUB-PCI—D30:F0)” on page 8-268
Section 8.1.24, “BRIDGE_CNT—Bridge Control
Register (HUB-PCI—D30:F0)” on page 8-269
Section 8.1.27, “CNF—ICH3 Configuration Register
(HUB-PCI—D30:F0)” on page 8-271
Section 8.1.28, “MTT—Multi-Transaction Timer Register
(HUB-PCI—D30:F0)” on page 8-271
Section 8.1.29, “PCI_MAST_STS—PCI Master Status
Register (HUB-PCI—D30:F0)” on page 8-272
Section 8.1.30, “ERR_CMD—Error Command Register
(HUB-PCI—D30:F0)” on page 8-272
Section 8.1.31, “ERR_STS—Error Status Register
(HUB-PCI—D30:F0)” on page 8-273
LPC Bridge D31:F0
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Eh
40–43h
Section 9.1.1, “VID—Vendor ID Register (LPC I/F—
D31:F0)” on page 9-276
Section 9.1.2, “DID—Device ID Register (LPC I/F—
D31:F0)” on page 9-276
Section 9.1.3, “PCICMD—PCI COMMAND Register
(LPC I/F—D31:F0)” on page 9-277
Section 9.1.4, “PCISTA—PCI Device Status Register
(LPC I/F—D31:F0)” on page 9-278
Section 9.1.5, “REVID—Revision ID Register (LPC I/F—
D31:F0)” on page 9-278
Section 9.1.6, “PI—Programming Interface Register
(LPC I/F—D31:F0)” on page 9-279
Section 9.1.7, “SCC—Sub Class Code Register (LPC I/
F—D31:F0)” on page 9-279
Section 9.1.8, “BCC—Base Class Code Register (LPC I/
F—D31:F0)” on page 9-279
Section 9.1.9, “HEADTYP—Header Type Register (LPC
I/F—D31:F0)” on page 9-279
Section 9.1.10, “PMBASE—ACPI Base Address
Register (LPC I/F—D31:F0)” on page 9-280
Intel^® 82801CA ICH3-S Datasheet
497