82801CA Datasheet, PDF (222/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.18.1.23 Register Access
In the ICH3 implementation of the AC-link, up to two codecs can be connected to the SDOUT pin.
The following mechanism is used to address the primary and secondary codecs individually.
The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of
slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for
slots 1 and 2 must be set in slot 0, as shown in Table 5-100. Slot 1 is used to transmit the register
address, and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should
be valid since only an address is transmitted. For I/O reads only slot 1 valid bit is set, while for I/O
writes both slots 1 and 2 valid bits are set.
The secondary codec registers are accessed using slots 1 and 2 as described above, however the slot
valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bit 0 (bit 0 of slot 0) is set
to 1. This allows the secondary codec to monitor the slot valid bits of slots 1and 2, and bit 0 of slot
0 to determine if the access is directed to the secondary codec. If the register access is targeted to
the secondary codec, slot 1 and 2 will contain the address and data for the register access. Since
slots 1 and 2 are marked invalid, the primary codec will ignore these accesses.
Table 5-100. Output Tag Slot 0
Bit
Primary Access Secondary Access
Example
Example
Description
15
1
14
1
13
1
12:3
X
2
0
1:0
00
1
Frame Valid
0
Slot 1 Valid, Command Address bit (Primary codec only)
0
Slot 2 Valid, Command Data bit (Primary codec only)
X
Slot 3–12 Valid
0
Reserved
01
Codec ID (00 reserved for primary; 01 indicate secondary)
When accessing the codec registers, only one I/O cycle can be pending across the AC-link at any
time. The ICH3 implements write posting on I/O writes across the AC-link (i.e., writes across the
link are indicated as complete before they are actually sent across the link). In order to prevent a
second I/O write from occurring before the first one is complete, software must monitor the CAS
bit in the codec access semaphore register which indicates that a codec access is pending. Once the
CAS bit is cleared, then another codec access (read or write) can go through. The exception to this
being reads to offset 54h/D4h (slot 12) which are returned immediately with the most recently
received slot 12 data. Writes to offset 54h and D4h (primary and secondary codecs), get transmitted
across the AC-link in slots 1 and 2 as a normal register access. Slot 12 is also updated immediately
to reflect the data being written.
The controller will not issue back to back reads. It must get a response to the first read before
issuing a second. In addition, codec reads and writes are only executed once across the link, and are
not repeated.
222
Intel^® 82801CA ICH3-S Datasheet