82801CA Datasheet, PDF (287/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
Bit
Description
Enables I/O (x) Extension Enable (XAPIC_EN)—R/W.
0 = The I/O (x) APIC extensions are not supported.
7 1 = Enables the extra features (beyond standard I/O APIC) associated with the I/O (x) APIC.
NOTE: This bit is only valid if the APIC_EN bit is also set to 1.
Alternate Access Mode Enable (ALTACC_EN)—R/W.
6 ^{0 = ALT Access Mode Disabled (default). Alt Access Mode allows reads to otherwise unreadable}
registers and writes otherwise unwritable registers.
1 = ALT Access Mode Enable.
5:3 Reserved.
DMA Collection Buffer Enable (DCB_EN)— R/W.
2 _{0 = DCB disabled.}
1 = Enables DMA Collection Buffer (DCB) for LPC I/F and PC/PCI DMA.
Delayed Transaction Enable (DTE)—R/W.
1 _{0 = Delayed transactions disabled.}
1 = ICH3 enables delayed transactions for internal register, FWH and LPC I/F accesses.
Positive Decode Enable (POS_DEC_EN)—R/W.
0 = The ICH3 will perform subtractive decode on the PCI bus and forward the cycles to LPC I/F if
0
not to an internal register or other known target on LPC I/F. Accesses to internal registers and to
known LPC I/F devices will still be positively decoded.
1 = Enables ICH3 to only perform positive decode on the PCI bus.
Intel^® 82801CA ICH3-S Datasheet
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