82801CA Datasheet, PDF (330/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8
Power Management Registers (D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as
well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in
the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved
bit, the value should always be 0. Software should not attempt to use the value read from a reserved
bit, as it may not be consistently 1 or 0.
9.8.1 Power Management PCI Configuration Registers (D31:F0)
Table 9-8 shows a small part of the configuration space for PCI Device 31: Function 0. It includes
only those registers dedicated for power management.
Some of the registers are only used for Legacy Power management schemes.
Table 9-8. PCI Configuration Map (PM—D31:F0)
Offset
40–43h
44h
A0h
A2h
A4h
A8h
B8–BBh
C0h
C4–CAh
CCh
Mnemonic
Register Name/Function
ACPI_BASE
ACPI_CNTL
GEN_PMCON_1
ACPI Base Address
ACPI Control
General Power Management Configuration 1
GEN_PMCON_2 General Power Management Configuration 2
GEN_PMCON_3 General Power Management Configuration 3
STPCLK_DEL Stop Clock Delay Register
GPI_ROUT
GPI Route Control
TRP_FWD_EN I/O Monitor Trap Forwarding Enable
MON[n]_TRP_RNG I/O Monitor[4:7] Trap Range
MON_TRP_MSK I/O Monitor Trap Range Mask
Default
00000001h
00h
0000h
0000h
00h
0Dh
00000000h
00h
0000h
0000h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Intel^® 82801CA ICH3-S Datasheet