82801CA Datasheet, PDF (223/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.18.2 AC-Link Low Power Mode
The AC-link signals can be placed in a low-power mode. When the AC ’97 power-down register
(26h), is programmed to the appropriate value, both BIT_CLK and SDIN will be brought to, and
held at a logic low voltage level.
Figure 5-22. AC-Link Powerdown Timing
SYNC
BIT_CLK
SDOUT
slot 12
prev. frame
TAG
W rite to Data
0x20 PR4
SDIN
slot 12
prev. frame
TAG
Note:
BIT_CLK not to scale
AC_Link_Pw rdw n_Tim ing
BIT_CLK and SDIN transition low immediately following a write to the power-down register
(26h) with PR4. When the AC ’97 controller driver is at the point where it is ready to program the
AC-link into its low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio
output frame.
The AC ’97 controller also drives AC_SYNC, and SDOUT low after programming AC ’97 to this
low-power, halted mode
Once the codec has been instructed to halt BIT_CLK, a special wake up protocol must be used to
bring the AC-link to the active mode since normal output and input frames can not be
communicated in the absence of BIT_CLK. Once in a low-power mode, the ICH3 provides three
methods for waking up the AC-link; external wake event, cold reset and warm reset.
Note: Before entering any low-power mode where the link interface to the codec is expected to be
powered down while the rest of the system is awake, the software must set the “shut off” bit in the
control register.
Intel^® 82801CA ICH3-S Datasheet
223