82801CA Datasheet, PDF (170/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.15.3.2
5.15.3.3
Operation
Initial setup programming consists of enabling and performing the proper configuration of ICH3
and the IDE device for Ultra ATA/33 operation. For ICH3, this consists of enabling Synchronous
DMA mode and setting up appropriate Synchronous DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE programming model is
followed. Once programmed, the drive and ICH3 control the transfer of data via the Ultra ATA/33
protocol. The actual data transfer consists of three phases, a start-up phase, a data transfer phase,
and a burst termination phase.
The IDE device begins the start-up phase by asserting DMARQ signal. When ready to begin the
transfer, the ICH3 will assert DMACK# signal. When DMACK# signal is asserted, the host
controller will drive CS0# and CS1# inactive, DA0-DA2 low. For write cycles, the ICH3 will
deassert STOP, wait for the IDE device to assert DMARDY#, and then drive the first data word and
STROBE signal. For read cycles, the ICH3 will tri-state the DD lines, deassert STOP, and assert
DMARDY#. The IDE device will then send the first data word and STROBE.
The data transfer phase continues the burst transfers with the data transmitter (ICH3–writes, IDE
device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on
each rising and falling edge of STROBE. The transmitter can pause the burst by holding STROBE
high or low, resuming the burst by again toggling STROBE. The receiver can pause the burst by
deasserting DMARDY# and resumes the transfers by asserting DMARDY#. The ICH3 will pause
a burst transaction in order to prevent an internal line buffer over or under flow condition, resuming
once the condition has cleared. It may also pause a transaction if the current PRD byte count has
expired, resuming once it has fetched the next PRD.
The current burst can be terminated by either the transmitter or receiver. A burst termination
consists of a Stop Request, Stop Acknowledge and transfer of CRC data. The ICH3 can stop a burst
by asserting STOP, with the IDE device acknowledging by deasserting DMARQ. The IDE device
stops a burst by deasserting DMARQ and the ICH3 acknowledges by asserting STOP. The
transmitter then drives the STROBE signal to a high level. The ICH3 will then drive the CRC value
onto the DD lines and deassert DMACK#. The IDE device will latch the CRC value on rising edge
of DMACK#. The ICH3 will terminate a burst transfer if it needs to service the opposite IDE
channel, if a Programmed I/O (PIO) cycle is executed to the IDE channel currently running the
burst, or upon transferring the last data from the final PRD.
CRC Calculation
Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/33 transfers. The
CRC value is calculated for all data by both the ICH3 and the IDE device over the duration of the
Ultra ATA/33 burst transfer segment. This segment is defined as all data transferred with a valid
STROBE edge from DDACK# assertion to DDACK# deassertion. At the end of the transfer burst
segment, the ICH3 will drive the CRC value onto the DD[15:0] signals. It is then latched by the
IDE device on deassertion of DDACK#. The IDE device compares the ICH3 CRC value to its own
and reports an error if there is a mismatch.
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Intel^® 82801CA ICH3-S Datasheet