82801CA Datasheet, PDF (220/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.18.1.15 Input Slot 1: Status Address Port / Slot Request Bits
The status port is used to monitor status of codec functions including, but not limited to, mixer
settings and power management.
Slot 1 must echo the control register index, for historical reference, for the data to be returned in
slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in slot 0.
For multiple sample rate output, the codec examines its sample rate control registers, the state of its
FIFOs, and the incoming SDOUT tag bits at the beginning of each audio output frame to determine
which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current audio input
frame signal which output slots require data from the controller in the next audio output frame. For
fixed 48 kHz operation the SLOTREQ bits are always set active (low) and a sample is transferred
each frame.
For multiple sample rate input, the tag bit for each input slot indicates whether valid data is present
or not.
Table 5-99. Input Slot 1 Bit Definitions
Bit
Description
19 Reserved (Set to zero)
18:12 Control Register Index (Stuffed with zeros if tagged invalid)
11 Slot 3 Request: PCM Left Channel (see note 1)
10 Slot 4 Request: PCM Right Channel (see note 1)
9 Slot 5 Request: Modem Line 1
8 Slot 6 Request: PCM Center Channel (see note 1)
7 Slot 7 Request: PCM Left Surround (see note 1)
6 Slot 8 Request: PCM Right Surround (see note 1)
5 Slot 9 Request: PCM LFE Channel (see note 1)
4:2 Slot Request 10–12: Not Implemented
1:0 Reserved (Stuffed with zeros)
NOTES:
1. Slot 3 Request and Slot 4 Request bits must be the same value, i.e., set or cleared in tandem. This is also
true for the Slot 7 and Slot 8 Request bits, as well as the Slot 6 and Slot 9 Request bits.
As shown in Table 5-99, slot 1 delivers codec control register read address and multiple sample rate
slot request flags for all output slots of the controller. When a slot request bit is set by the codec, the
controller will return data in that slot in the next output frame. Slot request bits for slots 3 and 4 are
always set or cleared in tandem, i.e., both are set or cleared.
When set, the input slot 1 tag bit only pertains to Status Address Port data from a previous read.
SLOTREQ bits are always valid independent of the slot 1 tag bit.
5.18.1.16 Input Slot 2: Status Data Port
The status data port receives 16-bit control register read data.
• Bit [19:4]: Control Register Read Data
• Bit [3:0]: Reserved.
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Intel^® 82801CA ICH3-S Datasheet