82801CA Datasheet, PDF (143/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.7.1 Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type in the
SLP_TYP field and then setting the SLP_EN bit. The hardware will then attempt to gracefully
put the system into the corresponding Sleep state by first going to a C2 state. See
Section 5.12.6 for details on going to the C2 state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override
event. In this case the transition to the S5 state will be less graceful, since there will be no
dependencies on observing Stop-Grant cycles from the processor or on clocks other than the
RTC clock.
Table 5-40. Sleep Types
Sleep Type
Comment
S1
ICH3 asserts the STPCLK# signal. It also has the option to assert CPUSLP# signal. This will
lower the processor’s power consumption. No snooping is possible in this state.
ICH3 asserts SLP_S3#. The SLP_S3# signal will control the power to non-critical circuits.
S3
Power will only be retained to devices needed to wake from this sleeping state, as well as to
the memory.
S4
ICH3 asserts SLP_S3# and SLP_S5#. The SLP_S5# signal will shut off the power to the
memory subsystem. Only devices needed to wake from this state should be powered.
Same as S4. ICH3 asserts SLP_S3# and SLP_S5#. The SLP_S5# signal will shut off the
S5
power to the memory subsystem. Only devices needed to wake from this state should be
powered.
5.12.7.2
Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events will force the system to a
full on state (S0), although some non-critical subsystems might still be shut off and have to be
brought back manually. For example, the hard disk may be shut off during a sleep state, and have to
be enabled via a GPIO pin before it can be used.
Upon exit from the ICH3-controlled Sleep states, the WAK_STS bit is set. The possible causes of
Wake Events (and their restrictions) are shown in Table 5-41.
Intel^® 82801CA ICH3-S Datasheet
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