82801CA Datasheet, PDF (246/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.2.1
246
System Control Block Status Word Register
Offset Address: 00–01h
Default Value: 0000h
Attribute:
Size:
R/WC, RO
16 bits
The ICH3’s integrated LAN Controller places the status of its Command and Receive units and
interrupt indications in this register for the processor to read.
Bit
Description
Command Unit (CU) Executed (CX)—R/WC.
15 _{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.}
1 = Interrupt signaled because the CU has completed executing a command with its interrupt bit set.
Frame Received (FR)—R/WC.
14 _{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.}
1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame.
CU Not Active (CNA)—R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
13 ^{1 = The Command Unit left the Active state or entered the Idle state. There are 2 distinct states of}
the CU. When configured to generate CNA interrupt, the interrupt will be activated when the CU
leaves the Active state and enters either the Idle or the Suspended state. When configured to
generate CI interrupt, an interrupt will be generated only when the CU enters the Idle state.
Receive Not Ready (RNR)—R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
12 _{1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU}
Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame
Descriptor.
Management Data Interrupt (MDI)—R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
11 _{1 = Set when a Management Data Interface read or write cycle has completed. The management}
data interrupt is enabled through the interrupt enable bit (bit 29 in the management data interface
control register in the CSR).
Software Interrupt (SWI)—R/WC.
10 _{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.}
1 = Set when software generates an interrupt.
Early Receive (ER)—R/WC.
9 _{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.}
1 = Indicates the occurrence of an Early Receive Interrupt.
Flow Control Pause (FCP)—R/WC.
8 _{0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.}
1 = Indicates Flow Control Pause interrupt.
Command Unit Status (CUS)—RO.
00 = Idle
7:6 _{01 = Suspended}
10 = LPQ (Low Priority Queue) active
11 = HPQ (High Priority Queue) active
Receive Unit Status (RUS)—RO.
0000 = Idle
0001 = Suspended
0010 = No Resources
5:2 _{0011 = Reserved}
0100 = Ready
0101 = Reserved
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = Suspended with no more RBDs
1010 = No resources due to no more RBDs
1011 = Reserved
1100 = Ready with no RBDs present
1101 = Reserved
1110 = Reserved
1111 = Reserved
1:0 Reserved.
Intel^® 82801CA ICH3-S Datasheet