82801CA Datasheet, PDF (122/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.8.5 Processor System Bus Interrupt Delivery
5.8.5.1 Theory of Operation
For processors that support Processor System Bus interrupt delivery, the ICH3 has an option to let
the integrated I/O APIC behave as an I/O (x) APIC. In this case, it will deliver interrupt messages
to the processor in a parallel manner, rather than using the I/O APIC serial scheme. The ICH3 is
intended to be compatible with the I/O (x) APIC specification, Rev 1.1
This is done by the ICH3 writing (via the Hub Interface) to a memory location that is snooped by
the processor(s). The processor(s) snoop the cycle to know which interrupt goes active.
The processor enables the mode by setting the I/O APIC Enable (APIC_EN) bit and by setting the
DT bit in the I/O APIC ID Register.
The following sequence is used:
1. When the ICH3 detects an interrupt event (active edge for edge-triggered mode or a change for
level-triggered mode), it sets or resets the internal IRR bit associated with that interrupt.
2. Internally, the ICH3 requests to use the bus in a way that automatically flushes upstream
buffers. This can be internally implemented similar to a DMA device request.
3. The ICH3 then delivers the message by performing a write cycle to the appropriate address
with the appropriate data. The address and data formats are described below in Section 5.8.5.5.
Note: Processor System Bus Interrupt Delivery compatibility with processor clock control depends on
the processor, not the ICH3.
5.8.5.2
Edge-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.
5.8.5.3
Level-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.
If after the EOI the interrupt is still active, then another “Assert Message” is sent to indicate that the
interrupt is still active.
5.8.5.4
Registers Associated with Processor System Bus Interrupt Delivery
Capabilities Indication
The capability to support Processor System Bus interrupt delivery will be indicated via ACPI
configuration techniques. This involves the BIOS creating a data structure that gets reported to the
ACPI configuration software.
DT bit in the Boot Configuration Register
This enables the ICH3 to deliver interrupts as memory writes. This bit is ignored if the APIC mode
is not enabled.
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Intel^® 82801CA ICH3-S Datasheet