82801CA Datasheet, PDF (358/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.10 General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte I/O space.
The base offset for this space is selected by the GPIO_BAR register. Table 9-12 summarizes the
ICH3 GPIO implementation.
Table 9-12. Summary of GPIO Implementation
GPIO
Type
Alternate
Function
(Note 1)
Power
Well
Notes
GPIO[0]
Input
Only
REQ[A]#
GPIO[1]
Input REQ[B]# or
Only REQ[5]#
GPIO[2:5]
Input
Only
PIRQ[E:H]#
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9:10]
Input
Only
Input
Only
Input
Only
N/A
Unmuxed
Unmuxed
Unmuxed
N/A
GPIO[11]
Input
Only
SMBALERT#
GPIO[12]
Input
Only
Unmuxed
GPIO[13]
Input
Only
Unmuxed
GPIO[14:15] N/A N/A
GPIO[16]
Output
Only
GNT[A]#
GPIO[17]
Output GNT[B]# or
Only GNT[5]#
GPIO[18:19]
Output
Only
Unmuxed
GPIO[20]
Output
Only
Unmuxed
GPIO[21]
Output
Only
Unmuxed
GPIO[22]
GPIO[23
Output
Only
Output
Only
Unmuxed
Unmuxed
Core
GPIO_USE_SEL bit 0 enables REQ/GNT[A]# pair.
Input active status read from GPE1_STS register bit 0.
Input active high/low set through GPI_INV register bit 0.
Core
GPIO_USE_SEL bit 1 enables REQ/GNT[B]# pair (See
note 4).
Input active status read from GPE1_STS register bit 1.
Input active high/low set through GPI_INV register bit 1.
Core
GPIO_USE_SEL bits [2:5] enable PIRQ[E:H]#.
Input active status read from GPE1_STS reg. bits [2:5].
Input active high/low set through GPI_INV reg. bit [2:5].
Core
Input active status read from GPE1_STS register bit 6.
Input active high/low set through GPI_INV register bit 6.
Core
Input active status read from GPE1_STS register bit 7.
Input active high/low set through GPI_INV register bit 7
Resume
Input active status read from GPE1_STS register bit 8.
Input active high/low set through GPI_INV register bit 8.
N/A Not implemented
GPIO_USE_SEL bit 11 enables SMBALERT#
Resume Input active status read from GPE1_STS register bit 11.
Input active high/low set through GPI_INV register bit 11.
Resume
Input active status read from GPE1_STS register bit 12.
Input active high/low set through GPI_INV register bit 12.
Resume
Input active status read from GPE1_STS register bit 13.
Input active high/low set through GPI_INV register bit 13.
N/A Not Implemented
Core
Output controlled via GP_LVL register bit 16.
TTL driver output
Core
Output controlled via GP_LVL register bit 17.
TTL driver output
Core
Output controlled via GP_LVL register bits [18:19].
TTL driver output
Core
Output controlled via GP_LVL register bit 20.
TTL driver output
Core
This GPO defaults high. Output controlled via GP_LVL
register bit 21.
TTL driver output
Core
Output controlled via GP_LVL register bit [22].
Open-drain output
Core
Output controlled via GP_LVL register bit [23].
TTL driver output
358
Intel^® 82801CA ICH3-S Datasheet