82801CA Datasheet, PDF (126/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.9.5 Data Frame Format
Table 5-28 shows the format of the data frames. For the PCI interrupts (A–D), the output from the
ICH3 is ANDed with the PCI input signal. This way, the interrupt can be signaled via both the PCI
interrupt input signal and via the SERIRQ signal (they are shared).
Table 5-28. Data Frame Format
Data
Frame #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Interrupt
IRQ0
IRQ1
SMI#
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IOCHCK#
PCI INTA#
PCI INTB#
PCI INTC#
PCI INTD#
Clocks Past
Start Frame
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
Comment
Ignored. IRQ0 can only be generated via the internal 8524
Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.
Ignored. IRQ8# can only be generated internally or on ISA.
Ignored. IRQ13 can only be generated from FERR#
Do not include in BM IDE interrupt logic
Do not include in BM IDE interrupt logic
Same as ISA IOCHCK# going active.
Drive PIRQA#
Drive PIRQB#
Drive PIRQC#
Drive PIRQD#
126
Intel^® 82801CA ICH3-S Datasheet