82801CA Datasheet, PDF (210/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-95. Data Values for Slave Read Registers
Register Bits
Description
0
7:0 Reserved.
System Power State
1
2:0 000 = S0 001 = S1 010 = Reserved 011 = S3
100 = S4 101 = S5 110 = Reserved 111 = Reserved
1
7:3 Reserved
2
3:0 Frequency Strap Register
2
7:4 Reserved
3
5:0 Watchdog Timer current value
3
7:6 Reserved
4
0
1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has
probably been opened.
4
1
1 = BTI Temperature Event occurred. This bit will be set if the ICH3’s THRM# input signal is
active. Need to take after polarity control.
4
2 Boot-Status. This bit will be 1 when boot failed
4
3
This bit will be set after the TCO timer times out a second time (Both TIMEOUT and
SECOND_TO_STS bits set).
4
6:4 Reserved.
The bit will reflect the state of the GPI[11]/SMBALERT# signal, and will depend on the
GP_INV[11] bit. It does not matter if the pin is configured as GPI[11] or SMBALERT#.
4
7
• If the GP_INV[11] bit is 1 then the value of register 4, bit 7 will equal the level of the
GPI[11]/SMBALERT# pin (high = 1, low = 0).
• If the GP_INV[11] bit is 0 then the value of register 4, bit 7 will equal the inverse of the
level of the GPI[11]/SMBALERT# pin (high = 1, low = 0).
5
0
Unprogrammed FWH bit. This bit will be 1 to indicate that the first BIOS fetch returned FFh,
which indicates that the FWH is probably blank.
5
7:1 Reserved
6
7:0 Contents of the Message 1 register. See Section 9.9.10.
7
7:0 Contents of the Message 2 register. See Section 9.9.10.
8
9–FFh
7:0 Contents of the WDSTATUS register. See Section 9.9.11.
7:0 Reserved
5.17.6.2.1 Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a start bit–address–
write bit sequence. When the ICH3 detects that the address matches the value in the Receive Slave
Address Register, it will assume that the protocol is always followed and ignore the write bit (bit 9)
and signal an Acknowledge during bit 10 (See Table 5-91 and Table 5-94). In other words, if a
Start–Address–Read occurs (which is illegal for SMBus Read or Write protocol), and the address
matches the ICH3’s Slave Address, the ICH3 will still grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–Read
sequence beginning at bit 20 (See Table 5-94). Once again, if the Address matches the ICH3’s
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with
the Slave Read cycle.
Note: An external microcontroller must not attempt to access the ICH3’s SMBus Slave logic until at least
1 second after both RTCRST# and RSMRST# are deasserted (high).
210
Intel^® 82801CA ICH3-S Datasheet