82801CA Datasheet, PDF (63/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Intel^® ICH3 and System Clock Domains
Intel^® ICH3 and System Clock Domains4
Table 4-1 describes the system clock domains. Figure 4-1 shows the assumed connection of the
various system components, including the clock generator. For complete details of the system
clocking solution refer to the system’s clock generator component specification.
Table 4-1. Intel^® ICH3 and System Clock Domains
Clock
Domain
Frequency
Source
Usage
ICH3
CLK66
ICH3
PCICLK
66 MHz
33 MHz
System PCI
33 MHz
ICH3
CLK48
48 MHz
ICH3
CLK14
14.31818 MHz
ICH3
AC_BIT_CLK
12.288 MHz
ICH3
APICCLK
33.33 MHz
LAN_CLK 5 to 50 MHz
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
Main Clock
Generator
AC ’97 Codec
Main Clock
Generator
LAN Connect
Component
Hub I/F, processor I/F, AGP. Shut off during S3 or below .
Free-running PCI Clock to ICH3. This clock remains on
during S0 and S1 state, and is expected to be shut off
during S3 or below in server configurations or .
PCI Bus, LPC I/F. These only go to external PCI and LPC
devices.
Super I/O, USB Controllers. Expected to be shut off
during S3 or below .
Expected to be shut off during S4 or below.
AC ’97 Link. Generated by AC ’97 Codec. Can be shut by
codec in D3. Expected to be shut off during S3 or below.
Used for ICH3-processor interrupt messages. Operates
up to 33.33 MHz. Expected to be shut off during S3 or
below.
Generated by the LAN Connect component. Expected to
be shut off during S3 or below.
Figure 4-1. Conceptual System Clock Diagram
Intel^®
ICH3
AGP (66 MHz)
33 MHz
APIC CLK
14.31818 MHz
48 MHz
C lo c k
Gen.
PCI Clocks
(33 MHz)
14.31818 MHz
48 MHz
32 kHz
XTAL
12.288 MHz
50 MHz
AC’97 Codec(s)
LAN Connect
SUSCLK# (32 kHz)
Intel^® 82801CA ICH3-S Datasheet
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