82801CA Datasheet, PDF (499/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Table A-1. Intel^® ICH3 PCI Configuration Registers (Continued)
Register Name
LPC COM Port Decode Ranges
LPC FDD & LPT Decode Ranges
LPC Sound Decode Ranges
FWH Decode Enable 1 Register
LPC Generic Decode Range 1
LPC Enables
FWH Select 1 Register
LPC Generic Decode Range 2
FWH Select 2 Register
FWH Decode Enable 2 Register
Function Disable Register
Vendor ID
Device ID
Command Register
Device Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer
Header Type
Bus Master Base Address Register
Offset
Datasheet Section and Location
E0h
E1h
E2h
E3h
E4–E5h
E6–E7h
E8h
EC–EDh
F2h
Section 9.1.25, “COM_DEC—LPC I/F Communication
Port Decode Ranges Register (LPC I/F—D31:F0)” on
page 9-289
Section 9.1.26, “FDD/LPT_DEC—LPC I/F FDD & LPT
Decode Ranges Register (LPC I/F—D31:F0)” on
page 9-290
Section 9.1.27, “SND_DEC—LPC I/F Sound Decode
Ranges Register (LPC I/F—D31:F0)” on page 9-290
Section 9.1.28, “FWH_DEC_EN1—FWH Decode
Enable 1 Register (LPC I/F—D31:F0)” on page 9-291
Section 9.1.29, “GEN1_DEC—LPC I/F Generic Decode
Range 1 Register (LPC I/F—D31:F0)” on page 9-292
Section 9.1.30, “LPC_EN—LPC I/F Enables Register
(LPC I/F—D31:F0)” on page 9-292
Section 9.1.31, “FWH_SEL1—FWH Select 1 Register
(LPC I/F—D31:F0)” on page 9-294
Section 9.1.32, “GEN2_DEC—LPC I/F Generic Decode
Range 2 Register (LPC I/F—D31:F0)” on page 9-295
Section 9.1.33, “FWH_SEL2—FWH Select 2 Register
(LPC I/F—D31:F0)” on page 9-295
Section 9.1.34, “FWH_DEC_EN2—FWH Decode
Enable 2 Register (LPC I/F—D31:F0)” on page 9-296
Section 9.1.35, “FUNC_DIS—Function Disable Register
(LPC I/F—D31:F0)” on page 9-297
IDE Controller (D31:F1)
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Dh
0Eh
20–23h
Section 10.1.1, “VID—Vendor ID Register (IDE—
D31:F1)” on page 10-366
Section 10.1.2, “DID—Device ID Register (IDE—
D31:F1)” on page 10-366
Section 10.1.3, “CMD—Command Register (IDE—
D31:F1)” on page 10-366
Section 10.1.4, “STS—Device Status Register (IDE—
D31:F1)” on page 10-367
Section 10.1.5, “RID—Revision Identification Register
(IDE—D31:F1)” on page 10-367
Section 10.1.6, “PI—Programming Interface Register
(IDE—D31:F1)” on page 10-368
Section 10.1.7, “SCC—Sub Class Code Register (IDE—
D31:F1)” on page 10-368
Section 10.1.8, “BCC—Base Class Code Register
(IDE—D31:F1)” on page 10-368
Section 10.1.9, “MLT—Master Latency Timer Register
(IDE—D31:F1)” on page 10-368
Section 10.1.12, “SCMD_BAR—Secondary Command
Block Base Address Register (IDE D31:F1)” on
page 10-369
Intel^® 82801CA ICH3-S Datasheet
499