82801CA Datasheet, PDF (421/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
The Bus Master registers are located from offset + 00h to offset + 51h and reside in the AC ’97
controller. Accesses to these registers do not cause the cycle to be forwarded over the AC-link to
the codec.
In the case of the split codec implementation accesses to the different codecs are differentiated by
the controller by using address offsets 00h–7Fh for the primary codec and address offsets 80h–FEh
for the secondary codec.
The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the
same global registers in the audio and modem I/O space. Therefore a read/write to these registers in
either audio or modem I/O space affects the same physical register.
Bus Mastering registers exist in I/O space and reside in the AC ’97 controller. The three channels,
PCM in, PCM out, and Mic in, each have their own set of Bus Mastering registers. The following
register descriptions apply to all three channels. The register definition section titles use a generic
“x_” in front of the register to indicate that the register applies to all three channels. The naming
prefix convention used in Table 13-3 and in the register description I/O address is as follows:
PI = PCM in channel
PO = PCM out channel
MC = Mic in channel.
Intel^® 82801CA ICH3-S Datasheet
421