82801CA Datasheet, PDF (405/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

SMBus Controller Registers (D31:F3)
12.2.1
HST_STS—Host Status Register
Register Offset: 00h
Default Value: 00h
Attribute:
Size:
R/WC
8-bits
All status bits are set by hardware and cleared by the software writing a one to the particular bit
position. Writing a zero to any bit position has no effect.
Bit
Description
BYTE_DONE_STS—R/WC.
0 = Cleared by writing a 1 to the bit position.
7 _{1 = The ICH3 has received a byte (for Block Read commands) or if it has completed transmission}
of a byte (for Block Write commands). This bit will be set even on the last byte of the transfer. It
will not be set when transmission is due to the Alert On LAN* heartbeat.
INUSE_STS—R/WC (special). This bit is used as semaphore among various independent software
threads that may need to use the ICH3’s SMBus logic, and has no other effect on hardware.
6
0 = After a full PCI reset, a read to this bit returns a 0.
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next
read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0,
and will then own the usage of the host controller.
SMBALERT_STS—R/WC.
0 = Interrupt or SMI# was not generated by SMBALERT#.
5 1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by
software writing a 1 to the bit position or by RSMRST# going low.
If the signal is programmed as a GPIO, then this bit will never be set.
FAILED—R/WC.
4
0 = Cleared by writing a 1 to the bit position.
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to
the KILL bit being set to terminate the host transaction.
BUS_ERR—R/WC.
3 _{0 = Cleared by writing a 1 to the bit position.}
1 = The source of the interrupt of SMI# was a transaction collision.
DEV_ERR—R/WC.
The source of the interrupt or SMI# was due to one of the following:
• Illegal Command Field,
2
• Unclaimed Cycle (host initiated),
• Host Device Time-out Error.]
0 = Software resets this bit by writing a 1 to this location. The ICH3 will then deassert the interrupt
or SMI#.
INTR—R/WC (special). This bit can only be set by termination of a command. INTR is not
dependent on the INTREN bit of the Host Controller Register (offset 02h). It is only dependent on
the termination of the command. If the INTREN bit is not set, then the INTR bit will be set, although
1 ^{the interrupt will not be generated. Software can poll the INTR bit in this non-interrupt case.}
0 = Software resets this bit by writing 1 to this location. The ICH3 will then deassert the interrupt or
SMI#.
1 = The source of the interrupt or SMI# was the successful completion of its last command.
HOST_BUSY—RO.
0 = Cleared by the ICH3 when the current transaction is completed.
1 = Indicates that the ICH3 is running a command from the host interface. No SMB registers should
0
be accessed while this bit is set, except the BLOCK DATA BYTE Register. The BLOCK DATA
BYTE Register can be accessed when this bit is set only when the SMB_CMD bits in the Host
Control Register are programmed for Block command or I²C Read command. This is
necessary in order to check the BYTE_DONE_STS bit.
Intel^® 82801CA ICH3-S Datasheet
405