82801CA Datasheet, PDF (493/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Testability
Table 18-6. XOR Chain #4 (RTCRST# Asserted for 7 PCI Clocks While PWROK Active)
Pin Name
HI0
HICOMP
APICD0
APICD1
FERR#
SERIRQ
GPIO38
SPKR
GPIO41
GPIO39
GPIO40
GPIO43
Ball #
L22
K19
J20
J21
J22
H22
H21
H23
G21
G23
F23
E23
Notes
Pin Name
USBP5N
LAN_TXD2
LAN_TXD1
EE_SHCLK
LAN_RXD2
LAN_TXD0
EE_CS
LAN_RXD1
LAN_RXD0
EE_DIN
EE_DOUT
LAN_RSTSYNC
OC0#
Ball #
A14
A10
C10
D10
A9
B9
E9
A8
C8
D8
E8
D7
E12
Notes
Last in XOR Chain
XOR Chain #4
OUTPUT
Table 18-7. Signals Not in XOR Chain
Pin Name
RSMRST#
PWROK
RTCX1
RTCX2
VBIAS
RTCRST#
LAN_CLK
AC_BIT_CLK
Ball #
AA7
AA6
AC7
AC6
AB7
Y7
C9
B7
Notes
Pin Name
CLK14
CLK48
CLK66
APICCLK
PCICLK
INTRUDER#
LAN_RST#
Ball #
J23
F20
T19
J19
T5
Y6
Y5
Notes
Intel^® 82801CA ICH3-S Datasheet
493